1. Field of the Invention
The present invention relates to a method for forming copper interconnects in dielectric materials with low dielectric constant, and more specifically, to a method for applying dual damascene in the fabrication of a semiconductor device.
2. Description of the Prior Art
The use of copper interconnects with low-k dielectrics is actively pursued for multilevel interconnect technologies. For dual-damascene application, the first via integration scheme is not as sensitive to the lithographic alignment as the self-aligned scheme. However, the removal of photoresist residue inside the via without hurting the low-k materials will be a problem in the case of photoresist rework.
In fact, damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form conductive lines (metal interconnects). Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive contact (or via) openings are also formed. In the standard dual damascene process, a first oxide layer is deposited over a conductive structure. A hard mask is formed over the first oxide layer. A first patterned photoresist layer is formed on the hard mask. The hard mask is patterned using the first photoresist layer as a pattern. The first photoresist layer is removed.
A second oxide layer is then formed over the hard mask. A second patterned photoresist layer is formed over the second oxide layer. Both the first oxide layer and the second oxide layer are etched to form the dual damascene opening. The first oxide layer is etched using the hard mask as a pattern and the conductive structure as an etching stop. The second oxide layer is etched using the second photoresist layer as a pattern and the hard mask as an etching stop. The second photoresist layer is then stripped by oxygen plasma. However, the oxygen plasma damages the exposed surface of the first oxide layer and the second oxide layer within the dual damascene opening. Therefore, there is a need for an improved method for making a dual damascene contact.
Also, silicon chip technology has increased the need for multi-layer interconnect systems to provide higher density circuits, faster signal propagation and to allow direct silicon die attachment. To meet these new requirements, the dielectric material must have a low dielectric constant (preferably less than 5) to reduce signal propagation delay, and must have a thermal expansion coefficient close to the value for silicon to allow direct die attachment to the substrate.
Heretofore, most of the dielectric materials used in multi-layer circuits have been conventional thick film compositions. A typical circuit is constructed by sequentially printing, drying and firing functional thick film layers atop a ceramic substrate that is usually 92-96% wt.
The multiple steps required make this technology process intensive with the large number of process steps and yield losses attributing to high costs. Thick film technology nevertheless fills an important need in microelectronics and will continue to do so in the foreseeable future. Recently, dielectric thick film compositions with low dielectric constant have been introduced. However, ceramic substrates with thermal expansion coefficients equal to that of silicon are not readily available.
From the foregoing, it can be seen that there is a substantial need for a low temperature co-fireable tape dielectric which
(1) has a low dielectric constant (less than 5), PA1 (2) has a thermal expansion coefficient very close to the value for silicon, and PA1 (3) can be fired in air at a low temperature (less than 1000.degree. C.), thus permitting the use of high conductivity metallurgies.
Normally, the well-known low dielectrics in the semiconductor industry are made from organic materials or inorganic materials. These materials are named as low-dielectric constant materials and measured by value of k. Generally the value of k for organic materials is about 2 to 3 (k=2 to 3), and the value of k for inorganic materials is about 2 to 3.5 (k=2 to 3.5). When the chip size is much smaller due to shrinkage, the k value of the inter-metal dielectrics (IMD) or inter-layer dielectrics (ILD) in need is much lower.
Within the microelectronics industry, there is an ongoing trend toward miniaturization coupled with higher performance. The scaling of transistors toward smaller dimensions, higher speeds, and lower power has resulted in an urgent need for low constant inter-level insulators. Low dielectric constant inter-level dielectrics have already been identified as being critical to the realization of high performance integrated circuits. Thus, there exists a need in the microelectronics industry for a thermally stable, non-corrosive low dielectric constant polymer with good solvent resistance, high glass transition temperature, good mechanical performance and good adhesive properties, particularly to copper.